1. Field of the Invention
The present invention relates generally to a semiconductor device, and more particularly to a double-gate structure fin-type transistor wherein a projecting semiconductor region (generally called “fin” or “pillar”, hereinafter referred to as “pillar”) is formed on a major surface of a semiconductor substrate, and the pillar is provided with a gate electrode, a channel region, a source region, a drain region, etc.
2. Description of the Related Art
The development in semiconductor integrated circuits (ICs) is greatly dependent on scaling rules, which are excellent characteristics, of their structural components, MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors). The smaller the dimensions of each component or semiconductor device, the higher the integration density of components in a limited chip area. It is expected, however, that miniaturization based on conventional MOSFET technology will reach a limit in the near future. One of the factors is that off-leak current increases as the degree of miniaturization increases. If the power supply voltage is lowered due to reduction in device dimensions, the gate voltage (threshold voltage), at which the channel is rendered conductive, needs to be lowered accordingly. On the other hand, the ratio (sub-threshold coefficient) of the drain current to the gate voltage in the cut-off state is basically unchanged even if the device dimensions are reduced. Thus, the off-leak current increases. In addition, the off-leak current increases on the order of magnitude. For example, it is estimated that in CMOS logic circuits, if the gate length decreases to about 50 nm, the off-state power consumption due to off-leak current begins to surpass the on-state power consumption and then rises sharply. In such a case, because of a problem of heat production, the integration density cannot be increased even if the dimensions of each device component are reduced. In memory cells of a DRAM (Dynamic Random Access Memory), the magnitude of off-leak current poses a serious problem since it directly affects the voltage retaining performance of storage nodes. If the threshold voltage is raised in order to decrease the off-leak current, a sufficient drive current cannot be obtained. If the impurity concentration is increased according to the scaling rules, the leak current at the PN junction or channel surface increases. Hence, memory cells cannot be formed with the conventional MOSFET structure. As is understood from the above, in the future miniaturization of semiconductor ICs, it is imperative to solve the problem of how the off-leak current of the semiconductor device should be suppressed.
A prospective solution to the problem of off-leak current is a fin-type transistor.
Prior-art techniques relating to the control of off-leak current in the fin-type transistor are as follows:
1. A projecting semiconductor region and a substrate are insulated by an oxide film (Jpn. Pat. Appln. KOKAI Publication No. H02-263473).
2. A high-concentration region is provided under the pillar, thereby insulating the channel region and substrate (Jpn. Pat. Appln. KOKAI Publication No. H03-245573).
3. A high-concentration region is provided at a center of the pillar (Jpn. Pat. Appln. KOKAI Publication No. H03-245573).
4. An LDD (Lightly Doped Drain) structure is applied to the source/drain region (Jpn. Pat. Appln. KOKAI Publication No. H05-048109).
5. A source/drain region is set off relative to the gate electrode (Jpn. Pat. Appln. KOKAI Publication No. 2002-118255).
6. Source and drain regions are independently provided on both sides of the pillar (Jpn. Pat. Appln. KOKAI Publication No. H08-139325).
7. A distance between the source and drain regions is varied within the pillar (Jpn. Pat. Appln. KOKAI Publication No. 2002-118255).
Techniques 1 to 3 aim at reducing the leak current due to punch-through, from the standpoint of a current path. In the fin-type transistor, a punch-through current path may easily form in the vicinity of a substrate junction under the pillar, where the gate electrode does not cover, and in the central part of the pillar. In technique 1, the current path under the pillar is insulated by the oxide film. In technique 2, the current path is narrowed by raising a potential barrier in the current path. In technique 3, the current path in the central part of the pillar is similarly narrowed. Techniques 4 to 7 also relate to measures to cope with leak current due to punch-through. In technique 4, as in the conventional MOSFET structure, the drain is formed thin and shallow, thereby preventing lowering of a potential barrier in the channel. In technique 5, the current path between the drain and source is increased as a whole. In technique 6, the current path is increased in the central part of the pillar. In technique 7, the current path is increased mainly under the pillar.
Even if the above prior-art techniques are combined, however, it is difficult to realize a fin-type transistor that exhibits such a performance that off-leak current is 1×10−16 ampere or less, which is required for, e.g. a transistor of a DRAM memory cell. The reason is that the method of controlling the width between both side surfaces of the pillar is not specified, or the method, if specified, is unclear.
The specification of the width of the pillar will now be explained.
If the width of the pillar is too large, transistors on both sides of the pillar will operate independently, and the advantage of the fin-type transistor will obviously be lost. Therefore, the width of the pillar has to be decreased to some degree.
There are various opinions that the width of the pillar should be less than the gate length, less than 7/10 of the gate length, or less than ¼ of the gate length. On the other hand, there is known a fin-type transistor wherein the width of the pillar is limited to 2√{square root over (2)}(∈SφF/q·Nsub)1/2 or less, in consideration of the relation to the width of the depletion layer just under the gate. In this expression, ∈S is a dielectric constant of the material of the pillar, φF is a Fermi level of the same semiconductor material, q is an elementary charge, and Nsub is the concentration in the channel.
However, in the former empirical rule, the relation to the channel concentration is not included. In the latter specification, the relation to the gate length is not included. Thus, if the channel concentration is 1×1017 cm−3, it should suffice if the width of the pillar is about 0.3 μm according to the latter specification. However, according to the former empirical rule, e.g. the rule that the pillar width is less than the gate length, if the gate length is 0.1 μm, the pillar width (0.3 μm) is greater than the gate length (0.1 μm) and the former rule is not satisfied. This is because only the pillar width is excessively evaluated.
Besides the gate length and the concentration in the channel, there are other factors that determine the off-leak current. These include the thickness of the gate oxide film and the concentration in the source/drain region. There are no prior-art documents mentioning these factors. It is thus difficult to realize the performance associated with off-leak current, based on the conventional empirical rule or specification of the pillar width. On the other hand, if the pillar width is too small, it becomes difficult to control the threshold voltage by the concentration in the channel region. If the controllability of the threshold voltage by the concentration in the channel region lowers, the sole method for controlling the threshold voltage is to alter the material of the gate electrode. This leads to an increase in cost of device design and manufacture. In particular, in the transistor of the DRAM in which the concentration in the channel region cannot be increased, it is considered that the tolerable range of width of the pillar becomes narrow. However, there is to prior-art document mentioning this point.
As has been discussed above, even where the fin-type transistor structure is used, it is difficult in the prior art to realize such performance that the off-leak current is set at 1×1016 cm−3 or less, while satisfying the condition that the threshold voltage can be controlled by the concentration in the channel region. In the near future, this will inevitably lead to an increase in design and manufacturing costs of integrated circuits.